AMD's Venice is the first 2nm x86 server chip, but the stack doesn't fully ship until 2027

Date:
Mon, 27 Jul 2026 21:40:00 +0000

Description:
AMD's Zen 6 Venice EPYC is a 2nm, 256-core, 512-thread juggernaut which comes into play at the same time as Nvidia is gunning for the data center CPU market.

FULL STORY ======================================================================Copy link Facebook X Whatsapp Reddit Pinterest Flipboard Threads Email Share this article 0 Join the conversation Follow us Add us as a preferred source on Google Newsletter Subscribe to our newsletter AMD EPYC 9006 "Venice" offers mammoth 256-core, 512-thread configuration that incorporates up to 1GB of L3 cache and PCI-E 6.0 and 16 DDR5 memory channels under the hood It's the first time AMD's EPYC lineup sees high core count CPUs push past the 5GHz barrier AMD is claiming a win by stating that its newest EPYC CPU offers the "most agents per watt, per dollar, per rack" AMD 's newly-announced 6th Gen EPYC 9006 "Venice" seems to be a genuine silicon milestone (the first x86 server CPU on a 2nm-class node, up to 256 cores and 512 threads) which sees the company aim to secure its position in the AI data center CPU market.

The launch comes at a time when AMD has caught Intel on the back foot but finds its position threatened in turn by Nvidia's Vera CPU , which it touts
as a faster, more efficient alternative to traditional x86 offerings, including AMD's own EPYC lineup. With a staggered launch in place for the
four CPUs AMD showcased at the AAI event, the stack is expected to be fully available to consumers sometime in 2027, even as its beefy 256-core CPU targets a Q4 2026 launch. Latest Videos From TechRadar Watch full video here: A massive upgrade on multiple fronts AMD's Venice is a serious generational step. It is built on TSMC's N2 process, the foundry's first move from FinFET to gate-all-around nanosheet transistors, and Team Red says the family is the first high-performance computing product in the industry to reach volume production on the node.

AMD's recently announced flagship model, the 256-core, 512-thread EPYC 9996, features its new SP7 socket, offering 16-channel DDR5 memory, PCIe 6.0 support, and boost clocks that push past 5GHz. You may like HP packs 81,920 CPU cores, up to 1.28PB RAM into one 42U rack using 80 multi-node
motherboards One of AMD's most powerful CPUs gets a 60% price cut Nvidia reveals deep dive into what makes Vera CPU tick

This effectively doubles what is currently on offer for AMD's current-gen
EPYC CPUs: memory moves to 16 channels of DDR5-8000, or MRDIMM at 12,800
MT/s, for roughly 1.6 TB/s per socket.

AMD goes one step further with the 9006X lineup (expected 2H 2027), which replaces the cores it cuts down on with a much larger L3 cache per core, a design that it touts makes it much better than rivals at workflows including HPC, technical computing, and data-intensive workloads, which benefit from
the larger cache (and memory bandwidth) on offer. Are you a pro? Subscribe to our newsletter Sign up to the TechRadar Pro newsletter to get all the top news, opinion, features and guidance your business needs to succeed! Contact me with news and offers from other Future brands Receive email from us on behalf of our trusted partners or sponsors By submitting your information you agree to the Terms & Conditions and Privacy Policy and are aged 16 or over.

6th Gen AMD EPYC delivers workload-optimized compute for the full spectrum of modern data center needs; from running more agents and feeding GPUs across rack-scale AI infrastructure to powering the business-critical applications and services organizations rely on every day," noted SVP & GM of Compute and Enterprise AI at AMD, Dan McNamara.

AMD argues that the shape of the data center is changing into a three-tier agentic architecture, with each tier creating distinct CPU demand, which results in workflows centering around agent sandbox execution, AI host nodes, and general-purpose servers, all of which its EPYC CPUs are designed to handle.

The EPYC 9006 series also powers AMD's rack-scale Helios, as it aims to take on Nvidia 's Vera Rubin NVL72 rack-scale offering with its own solution.

With AMD also offering a more mainstream 9006 SP8 and the EYPC 9006 LP as an AI host node CPU that uses LPDDR memory, it is aiming to capture all ends of the AI data center CPU market and cement its current lead in a segment that
is sure to be increasingly competitive in the days to come. Follow TechRadar on Google News and add us as a preferred source to get our expert news, reviews, and opinion in your feeds.



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Link to news story: https://www.techradar.com/pro/amds-venice-is-the-first-2nm-x86-server-chip-but -the-stack-doesnt-fully-ship-until-2027


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